In current complementary metal-oxide semiconductor (CMOS) scaling, the use of undoped gate all around (GAA) nanowire devices is a highly investigated structure as a device choice for future CMOS. One key problem with undoped devices is the implementation of multiple threshold voltage (Vt) devices. One solution is to dope the nanowire FET. To do so, however, for aggressively scaled devices has serious drawbacks from random dopant fluctuation (RDF) effects and becomes extremely problematic as the nanowire diameter is scaled. One can also engineer gate stacks with different work functions for different Vt's. This however requires a substantial amount of process complexity.
Therefore, improved techniques for fabricating multiple Vt nanowire FET devices that avoid the above-described drawbacks would be desirable.